1. Field of the Invention
The present invention relates to the field of computer system memory. More specifically, the present invention relates to an apparatus for integrating standard page mode dynamic random access memory (DRAM) devices with extended data-out DRAMs and a method for distinguishing between the type of DRAM populated in a memory subsystem in a computer system.
2. Description of Related Art
Personal computer systems are becoming increasingly more powerful and less expensive. At present, personal computer systems are achieving processing performance levels previously achieved only by mini-computers. And as the demand for high performance computers continues to grow, system designers will develop faster and more powerful microprocessors.
As microprocessors become increasingly faster, the speed of memory devices continue to be a major limiting factor in determining the performance of the computer systems. Specifically the memory speed can limit how fast application programs will run. While fast memory devices such as static random access memory (SRAM) devices are available, their use in main memory in a computer system is not common due to the relatively high cost of these memory devices.
Most system designers use dynamic random access memory (DRAMs) devices in main memory due to their relatively low cost and low power consumption. However, the slower speed of DRAMs tend to impede the performance of high performance microprocessor based computers.
To improve the performance of the DRAM devices, many system designers use page mode DRAMs. In a paged memory device memory is typically accessed by the underlying processor of the computer system by issuing an address that selects a particular location in the memory array. The address is then loaded into a memory controller which handles the task of providing row and column addresses used by the DRAM from the address provided by the processor.
After receiving an address from the processor, the memory controller places the row and then the column address on the DRAM""s address bus in response to the timing requirements of the DRAM. In prior art computer systems using standard page mode DRAMs, the microprocessor issues a full address to access a specific memory location via the memory controller. To handle address requests to main memory, prior art memory controllers include latches to temporarily retain previous address requests from the processor which are then compared with incoming addresses to determine if the DRAM""s row and column addresses have changed between successive memory requests.
In addition to the memory controller retaining addresses, the DRAMs retain data which require periodic refreshes. Refreshing the DRAM delays data fetches from a page in the DRAM due to the reasserting of control signals to the DRAM to reinitiate memory accesses in progress prior to a refresh cycle. Specifically, the row address strobe signal (RAS#) to the DRAM must be reasserted to reopen the page being accessed prior to the refresh. In reopening the page, the falling edge of the column address strobe (CAS#) is used to strobe a column address in the DRAM. Strobing the column address requires that CAS# be deasserted for a period typically referred to as precharge period. There is a minimum time between precharge and the next data being made available by the DRAM. The DRAM turns off its output signals when the CAS# is high requiring that the CAS# stays low until data is captured by the memory controller thereby delaying the precharge and subsequent availability of the next piece of data from the DRAM. This causes delays that cause wait states in a read cycle and thus slow down the performance of the underlying processor.
To alleviate the delays caused in accessing data due to the CAS# precharge time, system designers use a fast performance DRAM device known as the Extended Data Out DRAM (EDO DRAM) which have the same packaging and power characteristics as the page mode DRAMs and do not tristate the data output when CAS is deasserted, but have different timing requirements than the standard page mode DRAMs and do not cause the delays after a refresh cycle that are characteristic of the standard page mode DRAMS.
Although various types and sizes of the DRAMs (e.g., EDO DRAMs and the standard page mode DRAMs) may be installed in the memory subsystem in the computer, the computer must be configured properly in order to access the different types of DRAMs. In some prior art systems, the computer system is configured by use of hardware switches for specifying a plurality of memory configuration parameters. These parameters include the presence of a memory device in a particular bank, the type of memory device, and the size of the memory device. The use of hardware switches however requires the user to be knowledgeable of the various memory devices installed in the computer system.
Furthermore, despite performance advantage that the EDO DRAMs have over the current standard page mode DRAMs, system designers have not found a way to effectively integrate the EDO DRAMs into existing computer systems. Current implementations use either the standard page mode DRAMs or the EDO DRAMs. So, for example, if a computer user, who does not know much about the differences between memory devices, purchases a system designed to use the EDO DRAMs, the user may not be able to add a standard page mode DRAM purchased from the local computer store into the computer and derive the same performance if the computer had either all standard page mode DRAMs or EDO DRAMs. Mixing the two DRAM types slows performance because if the computer system is designed to take only standard page mode DRAMs, adding EDO DRAMs results in the EDO DRAMs using page mode DRAM timings or not working at all. On the other hand, if the computer user adds standard page mode DRAMs to a system designed for EDO DRAMs, the system will perform slowly because the memory controller is not able to distinguish between the EDO DRAM and the standard page mode DRAM due to the differences in the control and timing requirements of the two types of memory.
Thus, a system that effectively integrates and automatically configures various types of DRAM memory devices installed in the memory subsystem is needed.
The present invention provides a method and apparatus for integrating and distinguishing between memory banks populated with a standard page mode dynamic random access memory device (DRAM) or an extended data-out (EDO) DRAM in a memory subsystem. The preferred embodiment includes a plurality of configuration registersxe2x80x94each a bit widexe2x80x94having stored configuration information that identifies the type of DRAM device installed in a memory bank. Particularly, each configuration register corresponds to one or more rows of memory banks of DRAMs installed in the memory subsystem.
The preferred embodiment includes a DRAM bank decoder having decoding logic for decoding bank locations responsive to address requests from the processor in the computer system to the memory subsystem. The preferred embodiment further includes a detection logic circuit for detecting bits specified by the configuration registers corresponding to each memory bank populated with a DRAM device. The detection logic in combination with the decode logic determines whether memory bank locations in the memory subsystem is populated or not.
Memory access control signals comprising a row address strobe (RAS), a column address strobe (CAS), and an address strobe (ADS) are utilized by the preferred embodiment for control and timing requirements of the DRAM devices installed in the memory subsystem. A CAS state machine controls the various states of accesses to the DRAM devices. The CAS state machine in combination with the detection logic determines whether an address received by the memory subsystem is designated to the standard page mode DRAM or the EDO DRAM.
Advantages of the preferred embodiment of the present invention include the effective integration of various types of DRAM memory devices with different control and timing requirements in the same memory subsystem without degrading performance. The preferred embodiment also has the advantage of automatically storing information for identifying the type of memory device installed in a memory bank to spare the system user the inconvenience of determining the memory type and then manually setting hardware switches to configure memory.
The CAS state machine of the preferred embodiment allows memory access requests to either the standard page mode DRAM or the EDO DRAM without inserting an inordinate amount of wait states to slow the system down.
The features and advantages described in the specification are not all inclusive, and particularly, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification and claims hereof. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purpose, and therefore resort to the claims is necessary to determine the inventive subject matter.